Mercurial > cpython-lru_cache-weakref

annotate Lib/test/test_long.py @ 39042:c02fa187e0f4 legacy-trunk

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Part of SF patch #1484695. This removes dead code. The chksum was already verified in .frombuf() on the lines above. If there was a problem an exception is raised, so there was no way this condition could have been true.
author Neal Norwitz <nnorwitz@gmail.com>
date Mon, 10 Jul 2006 00:23:17 +0000
parents 27a718221e72
children 2551eb5671a4 6ba402b60041
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 import unittest
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2 from test import test_support
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3
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4 import random
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5
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6 # Used for lazy formatting of failure messages
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7 class Frm(object):
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8 def __init__(self, format, *args):
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9 self.format = format
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10 self.args = args
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11
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12 def __str__(self):
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13 return self.format % self.args
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14
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15 # SHIFT should match the value in longintrepr.h for best testing.
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16 SHIFT = 15
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17 BASE = 2 ** SHIFT
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18 MASK = BASE - 1
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19 KARATSUBA_CUTOFF = 70 # from longobject.c
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20
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21 # Max number of base BASE digits to use in test cases. Doubling
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22 # this will more than double the runtime.
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23 MAXDIGITS = 15
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24
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25 # build some special values
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26 special = map(long, [0, 1, 2, BASE, BASE >> 1])
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27 special.append(0x5555555555555555L)
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28 special.append(0xaaaaaaaaaaaaaaaaL)
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29 # some solid strings of one bits
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30 p2 = 4L # 0 and 1 already added
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31 for i in range(2*SHIFT):
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32 special.append(p2 - 1)
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33 p2 = p2 << 1
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34 del p2
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35 # add complements & negations
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36 special = special + map(lambda x: ~x, special) + \
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37 map(lambda x: -x, special)
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38
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39
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40 class LongTest(unittest.TestCase):
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41
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42 # Get quasi-random long consisting of ndigits digits (in base BASE).
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43 # quasi == the most-significant digit will not be 0, and the number
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44 # is constructed to contain long strings of 0 and 1 bits. These are
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45 # more likely than random bits to provoke digit-boundary errors.
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46 # The sign of the number is also random.
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47
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48 def getran(self, ndigits):
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49 self.assert_(ndigits > 0)
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50 nbits_hi = ndigits * SHIFT
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51 nbits_lo = nbits_hi - SHIFT + 1
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52 answer = 0L
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53 nbits = 0
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54 r = int(random.random() * (SHIFT * 2)) | 1 # force 1 bits to start
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55 while nbits < nbits_lo:
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56 bits = (r >> 1) + 1
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57 bits = min(bits, nbits_hi - nbits)
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58 self.assert_(1 <= bits <= SHIFT)
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59 nbits = nbits + bits
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60 answer = answer << bits
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61 if r & 1:
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62 answer = answer | ((1 << bits) - 1)
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63 r = int(random.random() * (SHIFT * 2))
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64 self.assert_(nbits_lo <= nbits <= nbits_hi)
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65 if random.random() < 0.5:
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66 answer = -answer
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67 return answer
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68
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69 # Get random long consisting of ndigits random digits (relative to base
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70 # BASE). The sign bit is also random.
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71
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72 def getran2(ndigits):
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73 answer = 0L
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74 for i in xrange(ndigits):
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75 answer = (answer << SHIFT) | random.randint(0, MASK)
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76 if random.random() < 0.5:
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77 answer = -answer
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78 return answer
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79
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80 def check_division(self, x, y):
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81 eq = self.assertEqual
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82 q, r = divmod(x, y)
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83 q2, r2 = x//y, x%y
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84 pab, pba = x*y, y*x
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85 eq(pab, pba, Frm("multiplication does not commute for %r and %r", x, y))
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86 eq(q, q2, Frm("divmod returns different quotient than / for %r and %r", x, y))
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87 eq(r, r2, Frm("divmod returns different mod than %% for %r and %r", x, y))
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88 eq(x, q*y + r, Frm("x != q*y + r after divmod on x=%r, y=%r", x, y))
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89 if y > 0:
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90 self.assert_(0 <= r < y, Frm("bad mod from divmod on %r and %r", x, y))
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91 else:
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92 self.assert_(y < r <= 0, Frm("bad mod from divmod on %r and %r", x, y))
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93
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94 def test_division(self):
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95 digits = range(1, MAXDIGITS+1) + range(KARATSUBA_CUTOFF,
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96 KARATSUBA_CUTOFF + 14)
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97 digits.append(KARATSUBA_CUTOFF * 3)
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98 for lenx in digits:
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99 x = self.getran(lenx)
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100 for leny in digits:
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101 y = self.getran(leny) or 1L
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102 self.check_division(x, y)
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103
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104 def test_karatsuba(self):
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105 digits = range(1, 5) + range(KARATSUBA_CUTOFF, KARATSUBA_CUTOFF + 10)
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106 digits.extend([KARATSUBA_CUTOFF * 10, KARATSUBA_CUTOFF * 100])
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107
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108 bits = [digit * SHIFT for digit in digits]
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109
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110 # Test products of long strings of 1 bits -- (2**x-1)*(2**y-1) ==
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111 # 2**(x+y) - 2**x - 2**y + 1, so the proper result is easy to check.
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112 for abits in bits:
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113 a = (1L << abits) - 1
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114 for bbits in bits:
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115 if bbits < abits:
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116 continue
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117 b = (1L << bbits) - 1
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118 x = a * b
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119 y = ((1L << (abits + bbits)) -
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120 (1L << abits) -
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121 (1L << bbits) +
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122 1)
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123 self.assertEqual(x, y,
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124 Frm("bad result for a*b: a=%r, b=%r, x=%r, y=%r", a, b, x, y))
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125
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126 def check_bitop_identities_1(self, x):
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127 eq = self.assertEqual
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128 eq(x & 0, 0, Frm("x & 0 != 0 for x=%r", x))
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129 eq(x | 0, x, Frm("x | 0 != x for x=%r", x))
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130 eq(x ^ 0, x, Frm("x ^ 0 != x for x=%r", x))
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131 eq(x & -1, x, Frm("x & -1 != x for x=%r", x))
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132 eq(x | -1, -1, Frm("x | -1 != -1 for x=%r", x))
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diff changeset
133 eq(x ^ -1, ~x, Frm("x ^ -1 != ~x for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
134 eq(x, ~~x, Frm("x != ~~x for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
135 eq(x & x, x, Frm("x & x != x for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
136 eq(x | x, x, Frm("x | x != x for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
137 eq(x ^ x, 0, Frm("x ^ x != 0 for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
138 eq(x & ~x, 0, Frm("x & ~x != 0 for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
139 eq(x | ~x, -1, Frm("x | ~x != -1 for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
140 eq(x ^ ~x, -1, Frm("x ^ ~x != -1 for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
141 eq(-x, 1 + ~x, Frm("not -x == 1 + ~x for x=%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
142 eq(-x, ~(x-1), Frm("not -x == ~(x-1) forx =%r", x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
143 for n in xrange(2*SHIFT):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
144 p2 = 2L ** n
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
145 eq(x << n >> n, x,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
146 Frm("x << n >> n != x for x=%r, n=%r", (x, n)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
147 eq(x // p2, x >> n,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
148 Frm("x // p2 != x >> n for x=%r n=%r p2=%r", (x, n, p2)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
149 eq(x * p2, x << n,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
150 Frm("x * p2 != x << n for x=%r n=%r p2=%r", (x, n, p2)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
151 eq(x & -p2, x >> n << n,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
152 Frm("not x & -p2 == x >> n << n for x=%r n=%r p2=%r", (x, n, p2)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
153 eq(x & -p2, x & ~(p2 - 1),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
154 Frm("not x & -p2 == x & ~(p2 - 1) for x=%r n=%r p2=%r", (x, n, p2)))
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
155
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
156 def check_bitop_identities_2(self, x, y):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
157 eq = self.assertEqual
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
158 eq(x & y, y & x, Frm("x & y != y & x for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
159 eq(x | y, y | x, Frm("x | y != y | x for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
160 eq(x ^ y, y ^ x, Frm("x ^ y != y ^ x for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
161 eq(x ^ y ^ x, y, Frm("x ^ y ^ x != y for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
162 eq(x & y, ~(~x | ~y), Frm("x & y != ~(~x | ~y) for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
163 eq(x | y, ~(~x & ~y), Frm("x | y != ~(~x & ~y) for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
164 eq(x ^ y, (x | y) & ~(x & y),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
165 Frm("x ^ y != (x | y) & ~(x & y) for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
166 eq(x ^ y, (x & ~y) | (~x & y),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
167 Frm("x ^ y == (x & ~y) | (~x & y) for x=%r, y=%r", (x, y)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
168 eq(x ^ y, (x | y) & (~x | ~y),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
169 Frm("x ^ y == (x | y) & (~x | ~y) for x=%r, y=%r", (x, y)))
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
170
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
171 def check_bitop_identities_3(self, x, y, z):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
172 eq = self.assertEqual
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
173 eq((x & y) & z, x & (y & z),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
174 Frm("(x & y) & z != x & (y & z) for x=%r, y=%r, z=%r", (x, y, z)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
175 eq((x | y) | z, x | (y | z),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
176 Frm("(x | y) | z != x | (y | z) for x=%r, y=%r, z=%r", (x, y, z)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
177 eq((x ^ y) ^ z, x ^ (y ^ z),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
178 Frm("(x ^ y) ^ z != x ^ (y ^ z) for x=%r, y=%r, z=%r", (x, y, z)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
179 eq(x & (y | z), (x & y) | (x & z),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
180 Frm("x & (y | z) != (x & y) | (x & z) for x=%r, y=%r, z=%r", (x, y, z)))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
181 eq(x | (y & z), (x | y) & (x | z),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
182 Frm("x | (y & z) != (x | y) & (x | z) for x=%r, y=%r, z=%r", (x, y, z)))
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
183
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
184 def test_bitop_identities(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
185 for x in special:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
186 self.check_bitop_identities_1(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
187 digits = xrange(1, MAXDIGITS+1)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
188 for lenx in digits:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
189 x = self.getran(lenx)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
190 self.check_bitop_identities_1(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
191 for leny in digits:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
192 y = self.getran(leny)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
193 self.check_bitop_identities_2(x, y)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
194 self.check_bitop_identities_3(x, y, self.getran((lenx + leny)//2))
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
195
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
196 def slow_format(self, x, base):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
197 if (x, base) == (0, 8):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
198 # this is an oddball!
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
199 return "0L"
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
200 digits = []
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
201 sign = 0
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
202 if x < 0:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
203 sign, x = 1, -x
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
204 while x:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
205 x, r = divmod(x, base)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
206 digits.append(int(r))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
207 digits.reverse()
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
208 digits = digits or [0]
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
209 return '-'[:sign] + \
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
210 {8: '0', 10: '', 16: '0x'}[base] + \
35177
27a718221e72 SF bug #1224347: int/long unification and hex()
Raymond Hettinger <python@rcn.com>
parents: 35072
diff changeset
211 "".join(map(lambda i: "0123456789abcdef"[i], digits)) + "L"
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
212
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
213 def check_format_1(self, x):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
214 for base, mapper in (8, oct), (10, repr), (16, hex):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
215 got = mapper(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
216 expected = self.slow_format(x, base)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
217 msg = Frm("%s returned %r but expected %r for %r",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
218 mapper.__name__, got, expected, x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
219 self.assertEqual(got, expected, msg)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
220 self.assertEqual(long(got, 0), x, Frm('long("%s", 0) != %r', got, x))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
221 # str() has to be checked a little differently since there's no
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
222 # trailing "L"
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
223 got = str(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
224 expected = self.slow_format(x, 10)[:-1]
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
225 msg = Frm("%s returned %r but expected %r for %r",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
226 mapper.__name__, got, expected, x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
227 self.assertEqual(got, expected, msg)
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
228
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
229 def test_format(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
230 for x in special:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
231 self.check_format_1(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
232 for i in xrange(10):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
233 for lenx in xrange(1, MAXDIGITS+1):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
234 x = self.getran(lenx)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
235 self.check_format_1(x)
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
236
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
237 def test_misc(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
238 import sys
9209
d3af310f230c New test_long.py from Tim Peters.
Guido van Rossum <guido@python.org>
parents: 8989
diff changeset
239
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
240 # check the extremes in int<->long conversion
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
241 hugepos = sys.maxint
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
242 hugeneg = -hugepos - 1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
243 hugepos_aslong = long(hugepos)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
244 hugeneg_aslong = long(hugeneg)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
245 self.assertEqual(hugepos, hugepos_aslong, "long(sys.maxint) != sys.maxint")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
246 self.assertEqual(hugeneg, hugeneg_aslong,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
247 "long(-sys.maxint-1) != -sys.maxint-1")
9209
d3af310f230c New test_long.py from Tim Peters.
Guido van Rossum <guido@python.org>
parents: 8989
diff changeset
248
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
249 # long -> int should not fail for hugepos_aslong or hugeneg_aslong
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
250 try:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
251 self.assertEqual(int(hugepos_aslong), hugepos,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
252 "converting sys.maxint to long and back to int fails")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
253 except OverflowError:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
254 self.fail("int(long(sys.maxint)) overflowed!")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
255 try:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
256 self.assertEqual(int(hugeneg_aslong), hugeneg,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
257 "converting -sys.maxint-1 to long and back to int fails")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
258 except OverflowError:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
259 self.fail("int(long(-sys.maxint-1)) overflowed!")
9209
d3af310f230c New test_long.py from Tim Peters.
Guido van Rossum <guido@python.org>
parents: 8989
diff changeset
260
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
261 # but long -> int should overflow for hugepos+1 and hugeneg-1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
262 x = hugepos_aslong + 1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
263 try:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
264 y = int(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
265 except OverflowError:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
266 self.fail("int(long(sys.maxint) + 1) mustn't overflow")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
267 self.assert_(isinstance(y, long),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
268 "int(long(sys.maxint) + 1) should have returned long")
9209
d3af310f230c New test_long.py from Tim Peters.
Guido van Rossum <guido@python.org>
parents: 8989
diff changeset
269
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
270 x = hugeneg_aslong - 1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
271 try:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
272 y = int(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
273 except OverflowError:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
274 self.fail("int(long(-sys.maxint-1) - 1) mustn't overflow")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
275 self.assert_(isinstance(y, long),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
276 "int(long(-sys.maxint-1) - 1) should have returned long")
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
277
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
278 class long2(long):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
279 pass
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
280 x = long2(1L<<100)
26291
d31ddc66b1b5 Change int() so that passing a string, unicode, float or long argument
Walter Dörwald <walter@livinglogic.de>
parents: 24794
diff changeset
281 y = int(x)
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
282 self.assert_(type(y) is long,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
283 "overflowing int conversion must return long not long subtype")
26291
d31ddc66b1b5 Change int() so that passing a string, unicode, float or long argument
Walter Dörwald <walter@livinglogic.de>
parents: 24794
diff changeset
284
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
285 # ----------------------------------- tests of auto int->long conversion
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
286
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
287 def test_auto_overflow(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
288 import math, sys
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
289
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
290 special = [0, 1, 2, 3, sys.maxint-1, sys.maxint, sys.maxint+1]
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
291 sqrt = int(math.sqrt(sys.maxint))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
292 special.extend([sqrt-1, sqrt, sqrt+1])
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
293 special.extend([-i for i in special])
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
294
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
295 def checkit(*args):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
296 # Heavy use of nested scopes here!
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
297 self.assertEqual(got, expected,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
298 Frm("for %r expected %r got %r", args, expected, got))
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
299
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
300 for x in special:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
301 longx = long(x)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
302
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
303 expected = -longx
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
304 got = -x
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
305 checkit('-', x)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
306
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
307 for y in special:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
308 longy = long(y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
309
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
310 expected = longx + longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
311 got = x + y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
312 checkit(x, '+', y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
313
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
314 expected = longx - longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
315 got = x - y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
316 checkit(x, '-', y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
317
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
318 expected = longx * longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
319 got = x * y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
320 checkit(x, '*', y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
321
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
322 if y:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
323 expected = longx / longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
324 got = x / y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
325 checkit(x, '/', y)
19459
50019cb784e0 Add a test for the new // operator too.
Tim Peters <tim.peters@gmail.com>
parents: 19458
diff changeset
326
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
327 expected = longx // longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
328 got = x // y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
329 checkit(x, '//', y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
330
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
331 expected = divmod(longx, longy)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
332 got = divmod(longx, longy)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
333 checkit(x, 'divmod', y)
19458
8f90e1f50c11 SF bug [#454456] int overflow code needs tests.
Tim Peters <tim.peters@gmail.com>
parents: 19452
diff changeset
334
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
335 if abs(y) < 5 and not (x == 0 and y < 0):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
336 expected = longx ** longy
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
337 got = x ** y
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
338 checkit(x, '**', y)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
339
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
340 for z in special:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
341 if z != 0 :
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
342 if y >= 0:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
343 expected = pow(longx, longy, long(z))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
344 got = pow(x, y, z)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
345 checkit('pow', x, y, '%', z)
19666
cf65ebf87560 New restriction on pow(x, y, z): If z is not None, x and y must be of
Tim Peters <tim.peters@gmail.com>
parents: 19459
diff changeset
346 else:
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
347 self.assertRaises(TypeError, pow,longx, longy, long(z))
19674
715244108faa Raise OverflowError when appropriate on long->float conversion. Most of
Tim Peters <tim.peters@gmail.com>
parents: 19666
diff changeset
348
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
349 def test_float_overflow(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
350 import math
19674
715244108faa Raise OverflowError when appropriate on long->float conversion. Most of
Tim Peters <tim.peters@gmail.com>
parents: 19666
diff changeset
351
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
352 for x in -2.0, -1.0, 0.0, 1.0, 2.0:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
353 self.assertEqual(float(long(x)), x)
19674
715244108faa Raise OverflowError when appropriate on long->float conversion. Most of
Tim Peters <tim.peters@gmail.com>
parents: 19666
diff changeset
354
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
355 shuge = '12345' * 120
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
356 huge = 1L << 30000
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
357 mhuge = -huge
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
358 namespace = {'huge': huge, 'mhuge': mhuge, 'shuge': shuge, 'math': math}
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
359 for test in ["float(huge)", "float(mhuge)",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
360 "complex(huge)", "complex(mhuge)",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
361 "complex(huge, 1)", "complex(mhuge, 1)",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
362 "complex(1, huge)", "complex(1, mhuge)",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
363 "1. + huge", "huge + 1.", "1. + mhuge", "mhuge + 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
364 "1. - huge", "huge - 1.", "1. - mhuge", "mhuge - 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
365 "1. * huge", "huge * 1.", "1. * mhuge", "mhuge * 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
366 "1. // huge", "huge // 1.", "1. // mhuge", "mhuge // 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
367 "1. / huge", "huge / 1.", "1. / mhuge", "mhuge / 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
368 "1. ** huge", "huge ** 1.", "1. ** mhuge", "mhuge ** 1.",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
369 "math.sin(huge)", "math.sin(mhuge)",
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
370 "math.sqrt(huge)", "math.sqrt(mhuge)", # should do better
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
371 "math.floor(huge)", "math.floor(mhuge)"]:
19679
6958784b1cef Whitespace normalization.
Tim Peters <tim.peters@gmail.com>
parents: 19674
diff changeset
372
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
373 self.assertRaises(OverflowError, eval, test, namespace)
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
374
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
375 # XXX Perhaps float(shuge) can raise OverflowError on some box?
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
376 # The comparison should not.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
377 self.assertNotEqual(float(shuge), int(shuge),
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
378 "float(shuge) should not equal int(shuge)")
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
379
35072
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Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
380 def test_logs(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
381 import math
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
382
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
383 LOG10E = math.log10(math.e)
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
384
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
385 for exp in range(10) + [100, 1000, 10000]:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
386 value = 10 ** exp
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
387 log10 = math.log10(value)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
388 self.assertAlmostEqual(log10, exp)
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
389
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
390 # log10(value) == exp, so log(value) == log10(value)/log10(e) ==
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
391 # exp/LOG10E
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
392 expected = exp / LOG10E
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
393 log = math.log(value)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
394 self.assertAlmostEqual(log, expected)
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
395
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
396 for bad in -(1L << 10000), -2L, 0L:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
397 self.assertRaises(ValueError, math.log, bad)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
398 self.assertRaises(ValueError, math.log10, bad)
19713
9433dd3c197e Return reasonable results for math.log(long) and math.log10(long) (we were
Tim Peters <tim.peters@gmail.com>
parents: 19698
diff changeset
399
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
400 def test_mixed_compares(self):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
401 eq = self.assertEqual
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
402 import math
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
403 import sys
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
404
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
405 # We're mostly concerned with that mixing floats and longs does the
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
406 # right stuff, even when longs are too large to fit in a float.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
407 # The safest way to check the results is to use an entirely different
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
408 # method, which we do here via a skeletal rational class (which
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
409 # represents all Python ints, longs and floats exactly).
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
410 class Rat:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
411 def __init__(self, value):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
412 if isinstance(value, (int, long)):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
413 self.n = value
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
414 self.d = 1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
415 elif isinstance(value, float):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
416 # Convert to exact rational equivalent.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
417 f, e = math.frexp(abs(value))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
418 assert f == 0 or 0.5 <= f < 1.0
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
419 # |value| = f * 2**e exactly
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
420
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
421 # Suck up CHUNK bits at a time; 28 is enough so that we suck
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
422 # up all bits in 2 iterations for all known binary double-
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
423 # precision formats, and small enough to fit in an int.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
424 CHUNK = 28
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
425 top = 0
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
426 # invariant: |value| = (top + f) * 2**e exactly
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
427 while f:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
428 f = math.ldexp(f, CHUNK)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
429 digit = int(f)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
430 assert digit >> CHUNK == 0
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
431 top = (top << CHUNK) | digit
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
432 f -= digit
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
433 assert 0.0 <= f < 1.0
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
434 e -= CHUNK
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
435
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
436 # Now |value| = top * 2**e exactly.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
437 if e >= 0:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
438 n = top << e
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
439 d = 1
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
440 else:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
441 n = top
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
442 d = 1 << -e
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
443 if value < 0:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
444 n = -n
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
445 self.n = n
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
446 self.d = d
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
447 assert float(n) / float(d) == value
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
448 else:
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
449 raise TypeError("can't deal with %r" % val)
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
450
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
451 def __cmp__(self, other):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
452 if not isinstance(other, Rat):
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
453 other = Rat(other)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
454 return cmp(self.n * other.d, self.d * other.n)
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
455
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
456 cases = [0, 0.001, 0.99, 1.0, 1.5, 1e20, 1e200]
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
457 # 2**48 is an important boundary in the internals. 2**53 is an
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
458 # important boundary for IEEE double precision.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
459 for t in 2.0**48, 2.0**50, 2.0**53:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
460 cases.extend([t - 1.0, t - 0.3, t, t + 0.3, t + 1.0,
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
461 long(t-1), long(t), long(t+1)])
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
462 cases.extend([0, 1, 2, sys.maxint, float(sys.maxint)])
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
463 # 1L<<20000 should exceed all double formats. long(1e200) is to
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
464 # check that we get equality with 1e200 above.
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
465 t = long(1e200)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
466 cases.extend([0L, 1L, 2L, 1L << 20000, t-1, t, t+1])
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
467 cases.extend([-x for x in cases])
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
468 for x in cases:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
469 Rx = Rat(x)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
470 for y in cases:
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
471 Ry = Rat(y)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
472 Rcmp = cmp(Rx, Ry)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
473 xycmp = cmp(x, y)
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
474 eq(Rcmp, xycmp, Frm("%r %r %d %d", x, y, Rcmp, xycmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
475 eq(x == y, Rcmp == 0, Frm("%r == %r %d", x, y, Rcmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
476 eq(x != y, Rcmp != 0, Frm("%r != %r %d", x, y, Rcmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
477 eq(x < y, Rcmp < 0, Frm("%r < %r %d", x, y, Rcmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
478 eq(x <= y, Rcmp <= 0, Frm("%r <= %r %d", x, y, Rcmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
479 eq(x > y, Rcmp > 0, Frm("%r > %r %d", x, y, Rcmp))
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
480 eq(x >= y, Rcmp >= 0, Frm("%r >= %r %d", x, y, Rcmp))
33547
702367da2c72 SF bug #513866: Float/long comparison anomaly.
Tim Peters <tim.peters@gmail.com>
parents: 33348
diff changeset
481
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
482 def test_main():
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
483 test_support.run_unittest(LongTest)
8989
5fb3c683e862 Add Tim Peters' test for long ints
Guido van Rossum <guido@python.org>
parents:
diff changeset
484
35072
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
485 if __name__ == "__main__":
5fb2163231d3 Port test_long.py to unittest.
Walter Dörwald <walter@livinglogic.de>
parents: 33547
diff changeset
486 test_main()